I have tried searching for an answer but to no avail, so given that my project has got the following structure
makefile ./src strings.cpp networking.cpp ./bin strings.dll networking.dll ./build strings.o networking.o ./include strings.h networking.h ./lib boost
I am very new to Makefiles and from the research I have done so far I have managed to get this together (not very complicated, I know)
CC = g++ SRC = src/strings.cpp OUT = bin/strings.dll OBJ = build/strings.o INC= -I include all: strings.dll strings.dll: strings.o $(CC) -shared -o $(OUT) $(OBJ) strings.o: $(SRC) $(CC) $(INC) -DBDLL -c $(SRC) -o $(OBJ)
The issues/questions I have are
1- It always goes through the whole compilation process, even when I have not changed the source code ?
2- How could I make things more ‘effective’ ? I saw examples of people using wildcards and such, but I had difficulty following along. Could I use wildcards to begin with since I want separate dlls for each target ?
3 – Lets say I introduced
algorithms.h and algorithms.cpp what would be the recommended way of including that in the build ?
Thanks for any help, really appreciate it